This invention relates to analog to digital (A/D) converters and more particularly, to a high speed analog subtraction circuit for use in A/D converters.
The most critical and usually the slowest function in a successive approximation A/D converter is the analog subtraction circuit. Typically an analog subtraction circuit consists of a high gain op amp which has an output connected to a series resistor. Since a highly accurate subtraction is required the gain of the op amp must also be quite high. As a direct result of the high gain required of the op amp RC time constant errors associated with op amp subtraction circuits severely limit their bandwidth. Even the most advanced high speed IC op amps have a gain bandwidth product on the order of 10 mHz. This relatively narrow bandwidth is a serious disadvantage when an extremely high speed, high accuracy subtraction circuit is required.
Therefore, it is a feature of this invention to provide an improved high speed analog subtraction circuit for use in an A/D converter which has a bandwidth of at least one hundred Megahertz.
It is another feature of this invention to provide a high speed analog subtraction circuit for use in an A/D converter which does not require an op amp with its associated gain and settling time errors.
It is yet another feature of the present invention to provide an analog subtraction circuit which uses a resistor to convert an analog current to an analog voltage.
It is still another feature of this invention to provide a high speed analog subtraction circuit for an A/D converter which has an internal voltage switching node which is clamped to minimize the voltage swing and parasitic capacitance at that node which thereby reduces the circuit RC time constant to approximately 1.2 nanoseconds.